1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. It is more particularly appropriate for the production of MOS or complementary MOS devices or the fabrication of bipolar transistors and complementary MOS transistors (BiCMOS) in the same semiconductor substrate.
2. Description of Related Art
In the fabrication of bipolar or MOS components, buried layers are firstly formed in the semiconductor substrate, generally made of silicon, these buried layers subsequently playing a specific role according to the component produced. Thus, the buried layers may especially be collectors for bipolar transistors, or else well bottom contacts for MOS transistors. These buried layers are characterized by their p-type or n-type doping so as to meet the specificities of the components that it is desired to produce (an npn or pnp bipolar transistor or an nMOS or pMOS transistor). Within the same semiconductor device, it is possible to encounter two adjacent MOS transistors of different conductivity (CMOS), two adjacent MOS transistors of the same conductivity separated by a region of opposite conductivity, and MOS transistors and bipolar transistors (BiCMOS).
Although being constituent elements of separate components, the buried layers within the same substrate cannot be doped independently of one another. This is because the doping levels of the buried layers determine, in particular, parasitic phenomena such as the breakdown voltage between p-type and n-type layers, and the punch-through voltage between layers of the same type of conductivity.
Thus, for example, the breakdown voltage between two layers of opposite conductivity is lower the greater the doping gradient between these layers. This is generally the case when the buried layers are highly doped.
Moreover, the risk of punch-through between buried layers of the same type is higher the shorter the distance separating the two layers. The separating region of opposite conductivity, which is not highly doped and is becoming narrower and narrower, can no longer fulfil its role of providing isolation between the two buried layers of the same type. The miniaturization of the integrated circuits necessarily leads to an increase in this risk.
To remedy the problem of punch-through, it would be conceivable to reduce the doping level of the layers of the same kind and increase that of the layers of opposite conductivity which separate them. This would in particular have the consequence of limiting the diffusion of the dopants from the highly doped layers into the lightly doped isolating layers. However, modification of the doping levels of the buried layers would also modify the intrinsic operation of the desired devices. Furthermore, if the doping of the separating layers is increased, there is also a risk of lowering the breakdown voltages.
With the reduction in size of the components and integrated circuits, it will become increasingly complicated to obtain a satisfactory compromise between the intrinsic operation of the devices and their isolation.
There is therefore a need to overcome these parasitic phenomena caused by the proximity of the components, and especially the contiguity of the buried layers.
More particularly, it seems to be necessary to provide solutions for minimizing, or indeed eliminating, the risk of punch-through of the buried layers and the lowering of the breakdown voltages, while still maintaining the proper intrinsic operation of the components produced.
The Applicant provides a solution which allows these problems to be remedied.
The invention essentially consists of the formation of buried trenches which laterally isolate, from one another, the buried layers of identical or different conductivities. In particular, it has been found that it is possible to prevent the immediate punch-through of the buried layers by adding such trenches in the semiconductor substrate between the layers. These trenches are positioned so as to separate the buried layers of different or identical conductivity from one another. These trenches form an obstacle to the diffusion of the dopants from one buried layer to another, and they also reduce the risk of lowering the breakdown voltage.
The proper intrinsic operation of the components is ensured because of independent doping of the buried layers of the device.
Thus, the invention provides an integrated circuit comprising a semiconductor substrate, for example made of silicon, including at least one dielectrically isolating, vertical buried trench having a height at least five times greater than its width, said trench laterally separating two regions, and an epitaxial semiconductor layer, for example made of single-crystal silicon, covering said trench.
The trenches prevent the diffusion of dopants through them, or else ensure galvanic isolation.
The trench must be narrow enough to allow the growth of a homogeneous epilayer over the entire surface of the semiconductor wafer. Preferably, the width of these trenches is less than 1 xcexcm, more preferably less than 0.3 xcexcm and more particularly about 0.2 xcexcm.
The depth of the trenches may vary depending on the requirement of the semiconductor device produced within the substrate.
As an indication, a trench may have a width of 0.2 microns and a height of greater than 5 microns, and may be buried at a depth of at least 0.8 microns.
Advantageously, the invention applies when there are at least three n, p and n or p, n and p adjacent buried layers, especially when it is desired to produce two MOS transistors of the same kind, the buried layers of which are separated by a region of opposite conductivity, or else in the case of BiCMOS technology since, in this situation, the risk of immediate punch-through of the buried layers may be high. The formation of narrow trenches, in order to laterally isolate the buried layers from one another, allows this risk to be greatly reduced or even eliminated.
Thus, according to one embodiment, the substrate includes at least two buried trenches and at least three adjacent buried regions of alternating conductivity, each of these buried regions being laterally separated from the region which is adjacent to it by a trench.
The substrate may include, approximately above the three buried regions of alternating conductivity, three epitaxial regions, having the same types of conductivity as the three buried regions respectively, and the circuit may include two MOS transistors of the same kind which are formed in the two epitaxial regions having the same type of conductivity.
As a variant, the circuit may include two MOS transistors of different kind which are formed in the two epitaxial regions having two different types of conductivity, respectively.
It may also furthermore include a bipolar transistor formed in the third epitaxial region.
The subject of the invention is also a process for fabricating an integrated circuit, comprising the formation of at least one dielectrically isolating, vertical buried trench in the semiconductor substrate of the circuit, said trench having a height at least five times greater than its width and laterally separating two regions, and the formation of an epitaxial semiconductor layer covering said trench.
The two regions may have conductivities of different type, which are obtained by implantation of dopants.
According to one method of implementation:
a) said trench is formed in the substrate;
b) the two regions having the same type of conductivity or else having two different types of conductivity are formed on each side of the trench by implantation;
c) an annealing operation is carried out; and
d) said epitaxial layer is grown, by epitaxy, on the structure obtained in step c).
The trench is preferably formed before the implantation of dopants in those regions of the substrate which are intended to subsequently form the buried layers. This is because, after this moment in the process, the thermal budget is less but there is less of a risk of the dopants diffusing from one layer to another. However, it may be envisaged to etch the trenches after implantation in specific cases that could require certain devices.
This implantation step is usually followed by an annealing operation in order to make the dopants diffuse, particularly over a thickness of preferably less than the depth of the trenches.
According to one method of implementation, a first single-crystal silicon layer is then grown epitaxially over the entire surface of the substrate. The very small size of the trenches allows almost homogeneous single-crystal silicon growth over the entire surface of the substrate.
It is possible to form, in this epitaxial single-crystal silicon layer, regions of the same conductivity as those of the subjacent buried layers and it is then advantageous to carry out an annealing operation so that there is continuity between the dopant in this epitaxial region and that in the buried region.
According to one method of implementation, prior to step b), the trenches are filled with a dielectric, preferably silicon oxide. It would also be possible to use nitride compounds or xe2x80x9cinsulator+conductorxe2x80x9d compounds such as, for example, silicon dioxide+polysilicon.
The process of the invention may advantageously be implemented in order to produce contiguous MOS and/or bipolar transistors, especially in BiCMOS and CMOS technologies.